1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and an efficient test method of the semiconductor integrated circuit device, where the semiconductor integrated circuit device, a SiP or especially PoP semiconductor integrated circuit device, enables a simultaneous testing of the reliability of multiple upper and lower semiconductor integrated circuit elements as well as an exchange only of a defective element for a non-defective unit in case any of the elements is defective; and similarly it enables an exchange of a defective element which occurs during a screening process such as burn-in.
2. Description of the Related Art
Recent development of mobile-phones, digital still cameras, digital video cameras, laptops and Personal Digital Assistants (PDA) demands smaller and lighter semiconductor integrated circuit devices, and the use of System in Package (SiP) that one external packaging is composed of multiple semiconductor integrated circuit devices has been growing. Among this SiP, the use of a Package on Package (PoP) has been increasing that one external packaging is composed by mounting at the back of a semiconductor integrated circuit device another semiconductor integrated circuit device.
It is required in the PoP that the upper semiconductor integrated circuit device and the lower semiconductor integrated circuit device should be tested simultaneously, but the simultaneous testing of multiple the upper and lower semiconductor integrated circuit devices is quite difficult because of the following reasons. A test of a PoP as a whole is conducted at terminals output at the undersurface of the lower semiconductor integrated circuit device; there are many cases that not all the terminals of the upper semiconductor integrated circuit device are output to the lower terminals since multiple semiconductor integrated circuit devices together composes a system LSI. Also, when the test detects a defect in any one of the upper and lower semiconductor integrated circuit devices, the both devices must be treated as a defect even though the other semiconductor integrated circuit device is non-defective. This is because the upper and lower semiconductor integrated circuit devices are not easily separated. As a result, the yield of the measuring test degrades exponentially. That is, when each of the upper and lower semiconductor integrated circuit devices has 90% of non-defectives, for example, the yield of the test is 90%×90%=81%. Similarly for the screening process such as burn-in, when any one of the upper and lower semiconductor integrated circuit devices is determined defective during the screening process, the both upper and lower semiconductor integrated circuit devices are treated as a defective since they cannot be easily separated as mentioned above. As a result, there is a problem that the yield of the screening process degrades exponentially.
Japanese Patent (JP-B) No. 2914308 proposes a test method of a semiconductor device that an interposer having a through-hole interposes between a semiconductor device and a test board to simplify the alignment of an electrode in the semiconductor device and a bump in the test board, and Japanese Patent Application Laid-Open (JP-A) No. 10-242350 proposes a mount structure of a bare chip that the bare chip is mounted on a circuit board through an interposer and that the bare chip may be easily removed in case the bare chip is defective. None of these, however, discloses an application to a SiP semiconductor integrated circuit device having multiple semiconductor integrated circuit devices. Regarding especially a PoP semiconductor integrated circuit device, a semiconductor integrated circuit device in which the both upper and lower semiconductor integrated circuit devices may be simultaneously tested and only a defect is exchangeable with a non-defect and an efficient test method of the semiconductor integrated circuit device have not yet been proposed.
The present invention resolves the existing problems mentioned above and aims at achieving the following objects. That is, the present invention provides a high-quality semiconductor integrated circuit device and an efficient test method of the semiconductor integrated circuit device, where the semiconductor integrated circuit device, a SiP or especially PoP semiconductor integrated circuit device, enables a simultaneous testing of the reliability of multiple upper and lower semiconductor integrated circuit elements; it also enables a testing of only the non-defective element in case the other is determined defective; moreover, only the defective unit is exchangeable with a non-defective unit; similarly when one becomes defective during a screening process such as burn-in, the process can be continued without regarding the other as defective.